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ORION

For more information about this sensor, please refer to the product page

1. Orion Sensor

1.1. Integration Time and Line Rate

Integration time is the time between falling egde RST_CDS and falling edge SAMPLE. 

To achieve 80 K lines per second please use an input clock of 100 MHz.

On a simplified way there is 2 things that limit the frame rate: the READOUT TIME and the ADC CONVERSION time. For this, keep in mind that for standard configuration the ADC clock is 2X the MAIN CLOCK and the Transmission data clock is 4X the Main clock. External 100 MHz = internal 50 MHz. 

  • Readout clocks = 560 in internal Main CLKs
  • ADC conversion = EOR*8 + 54 in internal Main CLKs

Having this in mind the integration time can be at maximum: Line rate time minus 1 us second or 50 clocks. 

1.2. Writing and Reading Registers to Sensor

To correctly write to sensor all timings must be active so to say MCLK must be provided .  The correct sequence is the following: 

  1. Write to Registers
  2. Send UPDATE request 
  3. Send Start READOUT 
  4. On the falling edge of LVAL the register will be updated .
  5. Read Registers
  6. Send UPDATE Request ( work around to solve the reading bug)

The spec says four extra clocks should be sent at the end of a write,  but we have implemented with 5 , but there is no problem with that.

You can perform the update at the end of the writes but I recommend you keep writing the update request after each individual register write. Writing a 0x06 to reg 0x1 can be done at the end of the writes

 

1.3. End of Range / ADC Gain Configuration

EORReg – End of Range Register Address: 0x06 setting has a linear relation with AGReg – Analogue Gain Register Address: 0x04 to get the 1V swing.  So for the each ADC resolution you have different Gains with master Clock 50 MHz :

Resolution Frame Rate ADC time EORReg Value(Hex) AGReg Value(Hex)
13 Bits 20 KHz 40 us FF CF
12 Bits 40 KHz 22 us 7F 9F
11 Bits 70 KHz 11 us 3F 40

 

 

 

 

1.4. Enhance Dynamic Range

Image sensors capable of a non-destructive readout (NDR) allow reading several frames during the integration time without affecting a photo charge being collected in the pixel's well .You should send a Start AD signal without sending the falling edge of SAMPLE and then send the Start readout  . You can do this several times without any problem . Basically to terminates one integration you should send the falling edge of SAMPLE if you don't do this the pixel will remain integrating.

1.5. Deserialization Questions

First Make sure that when you start up the sensor you follow the correct Power on Sequence described in the sensor specification;

For 2K and 4K Orion sensors all segments other than the 1st one are a little more troublesome to lock on due to the clock/data skew. On our USB3 evaluation board implementation (running with a MCLK of 80 MHz) we discard the incoming data clock and instead use an internally generated clock from a PLL to generate the necessary deserialization clocks. However, we do use a DPA architecture to delay the data paths for each LVDS pair. And afterwards perform the bitslip/word alignment.

Please check the register configuration sequence in the file attached.

Should only the "Valid" training pattern (8 training words before actual pixel data)  be used for bit alignment (i.e. bit slipping in the FPGA until the word is properly aligned) ?

  • Yes we synchronize data with the 8 training words . In our case we use AB AB AB AB AB AB AB AB that comes after the Start Readout falling edge. 

Is the Valid Training pattern used to detect valid video start and not bit alignment of the FPGA?  Does this give the ability to ignore the LVAL signal?

  • The LVAL is needed to identify the star of valid data  , the training sequence is used  just for bitslip (word alignment) . 

Does that mean that the bit alignment will change every line when START_READOUT is asserted?

  • Not at all , the Start_Readout  falling edge is latched with the Internal Main Clock , so basically if the Start_Readout is sent with a fixed period then the bit alignment will not change .

What is the usage of EXT_SYNC signal and how does that play in to things?

  • If the bit is active, then the readout sequencer counter is reset if a pulse is received  on the external sync line . This more a debug feature , in the case  this counter would be for some reason not working properly . In realty we don't use this feature.

Is the pattern at power up the same alternating A,B as described in the spec?

  • Yes it is the same , it will send the default values on the  registers TSQ1Reg TSQ2Reg . 

1.6. Select All Segments

If you write 0xF you will select all segments for register write/read. To Read this is not recommended but to write this is quite helpful .