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1.5. Deserialization Questions

First Make sure that when you start up the sensor you follow the correct Power on Sequence described in the sensor specification;

For 2K and 4K Orion sensors all segments other than the 1st one are a little more troublesome to lock on due to the clock/data skew. On our USB3 evaluation board implementation (running with a MCLK of 80 MHz) we discard the incoming data clock and instead use an internally generated clock from a PLL to generate the necessary deserialization clocks. However, we do use a DPA architecture to delay the data paths for each LVDS pair. And afterwards perform the bitslip/word alignment.

Please check the register configuration sequence in the file attached.

Should only the "Valid" training pattern (8 training words before actual pixel data)  be used for bit alignment (i.e. bit slipping in the FPGA until the word is properly aligned) ?

Is the Valid Training pattern used to detect valid video start and not bit alignment of the FPGA?  Does this give the ability to ignore the LVAL signal?

Does that mean that the bit alignment will change every line when START_READOUT is asserted?

What is the usage of EXT_SYNC signal and how does that play in to things?

Is the pattern at power up the same alternating A,B as described in the spec?

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